Title:
BUS CONTROL METHOD
Document Type and Number:
Japanese Patent JPS60178567
Kind Code:
A
Abstract:
PURPOSE: To obtain a rational and efficient access procedure by omitting access to a bus to which no channel is connected.
CONSTITUTION: Channels 4(0)W4(n) are connected to one CPU1 through an asynchronous bus 2, and channels 5(0)W5(n) are connected through a synchronous bus 3. Further, a means which informs the CPU1 that the channels 4(0)W4(n) and 5(0)W5(n) are not connected to buses 2 and 3 having a specific priority procedure is provided. When there is information on that, the CPU1 omits access to the buses.
Inventors:
KISHINO TAKUMI
HASHIMOTO SHIGERU
HASHIMOTO SHIGERU
Application Number:
JP3352084A
Publication Date:
September 12, 1985
Filing Date:
February 24, 1984
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G06F13/36; G06F13/42; (IPC1-7): G06F13/20
Attorney, Agent or Firm:
Sadaichi Igita