PURPOSE: To simplify maintenance such as exchange or the like and check by deciding an LSI generating a fault by providing a specified fault detecting circuit on the chip of each LSI.
CONSTITUTION: First and second pattern train output means 51b and 51c are provided to synchronize the same pattern train and to output it, the pattern train outputted by the output means 51b is inputted to a first judging means 51f after being delayed for prescribed time by a first delay circuit 51d and when the pattern train is not coincident with the pattern train outputted by the output means 51c, alarm information is outputted. On the other hand, when the pattern train outputted by the output means 51b is inputted to a second judging means 51g after being delayed for the longer delay time than that of the delay circuit 51d by a second delay circuit 51e, and when the judged result is not coincident, error information is outputted so as to stop the output of an objective logic circuit 40. Thus, the LSI generating the logic fault can be decided, and maintenance such as exchange or the like and check can be facilitated.
HAYASHI KENTARO
HAGIO MASAMI
OCHIAI TAKAYOSHI
