PURPOSE: To allow each processor to use a cache memory at the prescribed rate by dividing the overall area of a cache memory and constituting the divided area so that each processor will control and use the cache memory, setting the corresponding area as a governed area.

CONSTITUTION: A multi access controller 132, which controls in what sequence the access demand from the processors 129W131 shall be run, is provided between the processors 129W131 and the cache 102. A cache memory 112 is provided inside the cache 102. The entire area of the cache memory 112 is divided into the corresponding areas beforehand. The processors 129W131 use the cache memory 112, setting the corresponding area as a governed area.