PURPOSE: To generate a gate clock with extremely reduced clock skew by providing the titled circuit with a clock correcting circuit to find out AND between a gate clock and a free running clock.

CONSTITUTION: The titled circuit is provided with an oscillator, a gate circuit generating a gate clock and a free running clock by the output of the oscillator, the 1st delay circuit delaying the gate clock, and the 2nd delay circuit delaying the free running clock. For instance, an output generated from the oscillator 1 makes the gate circuit 2 generate a gate clock and a free running clock, the 1st delay circuit 6 delays the gate clock and the 2nd delay circuit 7 delays the free running clock. A clock correcting circuit 8 generates a newly corrected gate clock on the basis of the outputs of the 1st and 2nd delay circuits 6, 7 to find out AND between the signal from the circuit 8 and the free running clock.