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Title:
INVERTER CIRCUIT
Document Type and Number:
Japanese Patent JPS6041326
Kind Code:
A
Abstract:

PURPOSE: To make the operation speed higher and to reduce the power consumption by constituting a CMOS inverter of a P type MOS transistor Tr and an N type MOSTR to use this inverter as a bootstrap type.

CONSTITUTION: The first ∼ the third inverter circuits are constituted of N type MOSTRs 2, 4, and 6 as load elements and P type MOSTRs 1, 3, and 5 as driving elements. A prescribed input pulse in is inputted to the first and the second inverter circuits, and the first inverter circuit is allowed to fall after the fall of the output of the second inverter circuit. The output of the first inverter is applied to the gate of the TR5 of the third inverter. The output of the second inverter is applied to the gate of the TR6 of the third inverter through an earth potential and a P type MOSTR8. Thus, inverters are used as a bootstrap type to make the operation high-speed and to reduce the power consumption.


Inventors:
MASUDA HIROO
ICHINOMIYA MASANORI
Application Number:
JP14684184A
Publication Date:
March 05, 1985
Filing Date:
July 17, 1984
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03K19/0948; H03K17/06; H03K19/017; (IPC1-7): H03K17/06; H03K19/094
Domestic Patent References:
JPS56153836A1981-11-28
JPS51131255A1976-11-15
JPS5334701A1978-03-31
JPS5086967A1975-07-12
Attorney, Agent or Firm:
Katsuo Ogawa