Title:
MANUFACTURE OF LOW DISLOCATION COMPOUND SEMICONDUCTOR WAFER
Document Type and Number:
Japanese Patent JPS5815228
Kind Code:
A
Abstract:
PURPOSE:To fabricate low dislocation compound semiconductor wafers by a method wherein a three dimensional compound semiconductor layer is developed through epitaxial growth a compound semiconductor substrate, and then the objective low dislocation compound semiconductor is developed through epitaxial growth thereon. CONSTITUTION:After preprocessing such as etching, a GaAs substrate 2 is set in a substrate holder 1 made of graphite. Ga 20g, GaAs 3g and Al 50mg are put in a solution container 4 formed in a slide portion 3 made of graphite, while Ga 20g and GaAs 4g are put in another solution container 5. The surface of the substrate holder made of praphite is heated up to 950 deg. and the solution container 4 is disposed just above the substrate 2 so that the solution comes into contact with the substrate 2. In this state, the temperature of the entire graphite is cooled down 10 deg.C at a cooling speed of 0.1 deg.C/ mm.. When the surface temperature of the substrate holder reaches 850 deg.C, another solution container 5 is disposed just above the substrate 2 so that the solution comes into contact with the substrate 2. In this state, the entire graphite is cooled in its temperature down 40 deg.C at a cooling speed of 0.1 deg.C/mm. continuously. In such a manner, low dislocation compound semiconductor wafers can be fabricated with high yield.
Inventors:
TOYOSHIMA TOSHIYA
NAKAGAWA JIYUNKICHI
MIZUNIWA SEIJI
NAKAGAWA JIYUNKICHI
MIZUNIWA SEIJI
Application Number:
JP11416081A
Publication Date:
January 28, 1983
Filing Date:
July 21, 1981
Export Citation:
Assignee:
HITACHI CABLE
International Classes:
H01L21/208; C30B19/06; H01S5/00; (IPC1-7): H01L21/20; H01S3/18