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Title:
SEMICONDUCTOR INPUT BUFFER DEVICE
Document Type and Number:
Japanese Patent JPS5922443
Kind Code:
A
Abstract:

PURPOSE: To obtain a semiconductor input buffer device immune from noise and with low power consumption, by making the sum of an absolute value of the threshold voltage of a Pch FET constituting an input inverter circuit and the threshold voltage of an Nch FET greater than the power supply voltage of the inverter circuit.

CONSTITUTION: The source of a P-channel MOSFET3 constituting the input inverter circuit 1 is connected of its source to a power supply positive terminal and the drain is connected to an input terminal of an output inverter circuit 2. The source of an N-channel MOSFET 4 is connected to a power supply negative terminal 7 and the drain is connected to the drain of the MOSFET3 and an input terminal of the inverter circuit 2. Gates of the FETs 3, 4 are connected mutually and led to an input terminal 5. On the other hand, MOSFETs 6, 7 constituting the output inverter circuit 2 are connected in the same way as the inverter circuit 1, and the drains are connected together and led to an output terminal 8.


Inventors:
AKANUMA SHINICHI
Application Number:
JP13178882A
Publication Date:
February 04, 1984
Filing Date:
July 28, 1982
Export Citation:
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Assignee:
FUJI DENKI SOGO KENKYUSHO KK
FUJI ELECTRIC CO LTD
International Classes:
H03K19/0948; H03K19/003; H03K19/0185; (IPC1-7): H03K19/092
Attorney, Agent or Firm:
Iwao Yamaguchi



 
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