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Title:
PHASE LOCKED LOOP
Document Type and Number:
Japanese Patent JPS59186427
Kind Code:
A
Abstract:

PURPOSE: To hold loop characteristics of a PLL normally and to obtain an invariably stable readout clock by controlling the oscillation frequency range of a voltage-controlled oscillator by the output voltage of a bit rate detecting means.

CONSTITUTION: The phase locked loop PLL consists of a tape running speed detector 4 as a means for detecting the bit rate of data pulses Dp as an input signal, phase comparator 1, loop filter 2, and voltage-controlled oscillator 3 having the 1st and the 2nd control input terminals. The tape running speed detector 4 detects the rotating speed of capstan roller provided to a tape running system to obtain a voltage proportional to a tape running speed. For example, when a helical scanning type is used for a tape running mechanism, the tape running speed and output voltage, i.e. output voltage which corresponds to the bit rate of a playback signal, has a specific level even when the tape running speed is zero and is proportional to the tape running speed are obtained.


Inventors:
OGASAWARA YASUO
Application Number:
JP6172983A
Publication Date:
October 23, 1984
Filing Date:
April 08, 1983
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H03L7/113; H03L7/10; (IPC1-7): H03L7/10
Attorney, Agent or Firm:
Uchihara Shin



 
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