PURPOSE: To attain data reception with simple constitution by obtaining respectively a header and a final code from logical product among an FFH comparator, an 8-bit counter and a triggerable monostable multivibrator and logical product between the FFH comparator and the triggerable monostable multivibrator.

CONSTITUTION: A synchronizing clock detection circuit 3 latches an input data in bit synchronism to an input data pulse to be modulated and stores the data in 8-bit unit to a shift register 4. The data is compared with the FFH comparator 5 and logical "1" is outputted when the data is FFH. Further, the 7th bit of the input pulse is set to logical "1" in the counter 1 and while the 8-bit is reset to logical "0", a pulse having a width setting logical "1" is outputted. When it is detected that the output of the counter "1" is reset to logical "0", the retriggerable multivibrator 2 is reset to logical "0", and a pulse longer than, e.g., 1 byte is outputted. Then the header and final code are detected respectively from AND7 among the comparator 5, counter 1 and multivibrator 2 and AND6 between the comparator 5 and multivibrator 2.