PURPOSE: To complete main memory patrolling in a short time by connecting a 1 bit error flag and an error address register to a main memory, holding 1 bit error detected during arithmetic processing in the register and allowing CPU to detect an error easily when main memory patrolling which is carried out periodically.

CONSTITUTION: A 1 bit error flag 25 connected to an error detecting and correcting section 23 and an error address register 26 connected to an address register 21 are incorporated in SCU2 and input to a patrol controlling section 12 incorporated in CPU1 respectively. The 1 bit error flag 25 is normally in off state, and made on when data reading is made when arithmetic processing is made by CPU1 and when the error detecting and correcting section 23 detects 1 bit error, and informs of presence of 1 bit error in main memory patrolling. Further, the error address register 26 holds an address in which the error concerned is present when a bit error is detected.