Title:
DISPLAY CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS6061790
Kind Code:
A
Abstract:
There is provided a display control circuit including a central processing unit and display memory elements provided corresponding to respective data lines of the central processing unit. The display memory elements respectively have a plurality of data input terminals supplied with bit orders beforehand. As the display memory element, a large capacity readable/writable memory having a bit width per address such as 4 or 8 is used. Each bit per one address of said display memory element is assigned to an element belonging to each plane in the depth direction which constituted an individual picture element on the display screen. And one picture element is represented by one address of one display memory element. As a result, the number of display memory elements can be decreased.
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Inventors:
KOMATSU SHIGERU
IKEDA TETSUYA
IKEDA TETSUYA
Application Number:
JP16915683A
Publication Date:
April 09, 1985
Filing Date:
September 16, 1983
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G06F3/153; G09G5/00; G09G5/02; G09G5/39; (IPC1-7): G06F3/14; G09G1/02; G09G1/28
Domestic Patent References:
| JPS5810135B2 | 1983-02-24 |
Attorney, Agent or Firm:
Katsuo Ogawa