PURPOSE: To prevent a PLL from being locked in a π phase shifted state, by thinning pulses which are not in phase with initial synchronizing data, from a pulse waveform obtained by multiplying a received signal by two, with a mask signal.

CONSTITUTION: A reception input (1) is multiplied by two at a duplicating circuit 1 to obtain a duplicated output (2). When a PLL is locked with slanting- line pulses with a waveform (2), a π phase shift from the reception input (1) is caused as a waveform (3) (in abnormal state). A mask circuit 5 generates mask pulses (10) with the waveform (2) for masking the slanting-line pulses. The mask pulses (10) are supplied to a zero-cross level converter 3 through a BPF2 having a center frequency equal to the frequency of a timing signal, and it is converted into a pulse waveform with a 50% duty cycle. Then, the resulting signal is supplied to a digital PLL4, which outputs a timing signal (3).