PURPOSE: To reduce the data processing time by reading a parity bit of reception data from a terminal device in an integrated circuit for asnychronous transmission and reception.

CONSTITUTION: When the word length of a reception data R is (n-1) or no parity exists, a control signal S of a control register 115 becomes an ON-signal to bring the most significant bit of the reception data R to 0. When the word length of the content of the control register 115 is (n) or any parity exists, the control signal S becomes an OFF signal, the reception data R of a serial∼parallel circuit 118 is transmitted directly to a reception data register 117 and also the presence of the parity is displayed. The presence of the parity is displayed in this way and the parity is read, then the time for parity generation is not needed.