PURPOSE: To improve the efficiency of check by dividing bits of a register into the prescribed number of groups and comparing individually addresses as to each bit group.

CONSTITUTION: A register 11 storing a compared address and comparators 41W 43 comparing the compared address in the register 11 with an address to be detected from an address input terminal A1 are provided. A signal from the comparators 41W43 is fed to AND gates 51W53. The coincidence of addresses to a high-order bit of the register 11 is detected by an address coincidence detecting circuit 61 and also the coincidence of addresses to a low-order bit of the register 11 is detected by an address coincidence detecting circuit 63. Then the final address is detected by a detecting circuit 7. A mask signal of the high or low-order bit is set by registers 21, 22, and a gate signal is transmitted by a decoder 31 to the AND gates 51, 52 while receiving a signal from the register 21, further a signal from the register 21 is received via a gate 23 and a decoder 32 transmits a gate signal to the AND gate 53.