Title:
CMOS ARITHMETIC CIRCUITRY
Document Type and Number:
Japanese Patent JPS60110136
Kind Code:
A
Abstract:
PURPOSE:To obtain the layout method of an arithmetic circuitry which has advantages in area and performance by laying out power source lines and grounding lines with lower layer metallic wirings in a unit bit direction, and laying out control signal lines with upper layer metallic wirings in a direction perpendicular to the bit direction. CONSTITUTION:Lower layer metallic wirings 43, 42 are used to be readily connected with diffused layers for power source wirings 39, 31, grounding wirings 30. The larger the capacity between the power source wirings, the grounding wirings and substrates 48, 51 is, it is hardly affected by the influence of variations in the voltage of a power source. Further, even when the source side diffused layer of a transistor is connected with the power source or the grounding potential, contacting can be feasible. Lower layer metallic wirings are used for bus wirings 28, 32 parallel to the power source wirings and the grounding wirings. The bus wirings preferably have small capacity to the substrates, but when the metallic layer wirings are presumed, signal delays of the control signal lines 37, 38, 39 perpendicular to the bus wirings are critical. Accordingly, the lower layer wirings are employed. The lines 37 use upper layer metallic wirings 41.
Inventors:
NOGUCHI YOSHIKI
HAGIWARA YOSHIMUNE
TAKAHASHI TAMOTSU
KAMESHIMA SHIGEHIRO
HAGIWARA YOSHIMUNE
TAKAHASHI TAMOTSU
KAMESHIMA SHIGEHIRO
Application Number:
JP21775783A
Publication Date:
June 15, 1985
Filing Date:
November 21, 1983
Export Citation:
Assignee:
HITACHI LTD
HITACHI MICROCUMPUTER ENG
HITACHI MICROCUMPUTER ENG
International Classes:
H01L21/822; H01L21/768; H01L21/82; H01L21/8234; H01L21/8238; H01L27/04; H01L27/088; H01L27/092; (IPC1-7): H01L27/04; H01L27/08
Domestic Patent References:
| JPS57190343A | 1982-11-22 |
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)