Title:
SEQUENCE CONTROLLING DEVICE
Document Type and Number:
Japanese Patent JPS5979311
Kind Code:
A
Abstract:
PURPOSE:To enable high speed and low speed logical control in a body by dividing the content of sequence into high speed and low speed, forming a block by dispersing the low speed processing and combining with high speed processing, and prescribing the processing time of the block. CONSTITUTION:An input signal is divided into a low speed input section 11A and a high speed input section 11B, and high speed input information is stored in the RAM15 of a CPU9. In a system processing program, a low speed processing program is dispersed into plural programs, and a high speed processing program is combined to this to form blocks 16-N and stored in a ROM10. By setting the maximum time of running of the block smaller than the time of one pulse of input to be processed at high speed, high speed input signal can be followed up surely. In low speed processing, lines forming the sequence are controlled successively little by little, and after finishing control of the last line, the first block is controlled again, and this is repeated.
Inventors:
TAKAHASHI NARUYOSHI
UEDA AKIHISA
ABE RIYOUICHI
UEDA AKIHISA
ABE RIYOUICHI
Application Number:
JP18902682A
Publication Date:
May 08, 1984
Filing Date:
October 29, 1982
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G05B19/05; G05B19/042; (IPC1-7): G05B19/02
Attorney, Agent or Firm:
Toshiyuki Usuda
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