Title:
MULTIPLIER
Document Type and Number:
Japanese Patent JPS5831449
Kind Code:
A
Abstract:
PURPOSE: To improve the throughput of an array system multiplier by successively executing multiplication basing on parallel operation system like a pipe line system.
CONSTITUTION: A prestage operating circuit K is formed by half address 1W3 and full address 4W9 , a ripple charrying type counting circuit E is formed by full adders 10W12 and the prestage operating circuit K and the ripple carrying type counting circuit E are connected through a 10-bit register 13 for temporally storing the operation results of the operating circuit K. Consequently the operations of the operating circuit K and the ripple carrying type counting circuit E are operated simultaneously and the product data D1WD8 of multiplied results are stored in a register 14.
More Like This:
| JPH04281525 | MULTIPLYING CIRCUIT |
| JPS59173845 | QUINTUPLE CIRCUIT OF +- QUINARY NUMBER |
Inventors:
NODA MAKOTO
Application Number:
JP12872081A
Publication Date:
February 24, 1983
Filing Date:
August 19, 1981
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G06F7/53; G06F7/52; G06F7/527; (IPC1-7): G06F7/52
Domestic Patent References:
| JPS5672739A | 1981-06-17 |
Attorney, Agent or Firm:
Noriyuki Noriyuki