PURPOSE: To obtain a priority encoder circuit of which delay time is shortened by connecting an individual logic circuit without cascading in multi-stages and determining the upper bit output of the priority encoder circuit.

CONSTITUTION: In the figure, the numbers 43, 45, 47, 49 show signal lines to connect an enabling signal input EI of respective PE-B with the outputs D1, E2, E3, E4 of an enabling input signal determining circuit 35, and the numbers 44, 46, 48, 50 show signal lines to connect an enabling signal output EO of each priority encoder with the inputs G1, G2, G3, G4 of the enabling input signal determining circuit 35. In the circuit, an enabling signal is determined by the enabling input signal determining circuit 35 without transmitting like cascade between respective PE-Bs, so that the delay time until the output logic of Q0∼Q4 is determined can be shortened.