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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS615673
Kind Code:
A
Abstract:

PURPOSE: To attain ease of chip arrangement with high accuracy by constituting the titled device that a proper angle is given between two planes constituting the surface of the semiconductor chips of both rows in arranging plural semiconductor chips in zigzag at the position of two rows alternately.

CONSTITUTION: The semiconductor chips 1, 1' are arranged in zigzag on a chip fixed substrate 4. In this case, the surface of the substrate 4 is constituted to be not a plane but two planes having a proper angle and the chips are arranged one by one row on each plane so that each chip surface is in contact with the vicinity of the boundary line. Through the constitution above, the zigzag chip arrangement is attained depending only on the accuracy of size on the surface only to the chips where the surface and the side face have no right angle but an obtuse angle. Further, the chips on one row are arranged in a line in advance, then the other row is arranged easily with high accuracy while using the one row as a guide.


Inventors:
NAKAYAMA NOBUO
KOSEKI HIDEO
UEDA MASAAKI
DOBASHI NOBUHIRO
TOYONAGA YUUKO
YANO ISAMU
Application Number:
JP12521384A
Publication Date:
January 11, 1986
Filing Date:
June 20, 1984
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H04N1/028; H01L27/14; H01L27/146; (IPC1-7): H01L27/14; H04N1/028
Attorney, Agent or Firm:
Mototoshi Takeda (1 outside)