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Title:
CENTRAL PROCESSING UNIT SYSTEM PROVIDED WITH FALSE INSTRUCTION GENERATOR
Document Type and Number:
Japanese Patent JPS5930148
Kind Code:
A
Abstract:

PURPOSE: To simplify the constitution, by providing a false instruction on a CPU system having an external operator, so that timing given to the external operator is executed in the inside of the CPU.

CONSTITUTION: A program memory 3 sends out data information of a designated address to a false instruction generator 4. The false instruction generator 4 decodes and stores the data information from the program memory 3, and also sends out a false instruction of "Read a data from a data memory 2" to a data bus 8. The CPU 1 reads the false instruction from the data bus 8, sends out address information and control information to an address bus 7 and a control bus 6, respectively, in order to read the data from the data memory 2, and designates the prescribed address of the data memory 2. The false instruction generator 4 gives a command to the external operator 5 with respect to an executing operation of an instruction which the generator itself stores, and the external operator 5 inputs the information on the data bus 8 to calculate.


Inventors:
HARA KENJI
Application Number:
JP14082282A
Publication Date:
February 17, 1984
Filing Date:
August 11, 1982
Export Citation:
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Assignee:
YASKAWA DENKI SEISAKUSHO KK
International Classes:
G06F9/38; G06F9/30; (IPC1-7): G06F9/30
Attorney, Agent or Firm:
Yoshihiro Imai