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Patent Searching and Data


Title:
COMPLEMENTARY MOS DEVICE
Document Type and Number:
Japanese Patent JPS6132463
Kind Code:
A
Abstract:

PURPOSE: To obtain the titled device excellent in latch-up withstand voltage by a method wherein P+ type source-drain diffused regions or N+ type source-drain diffused regions are constructed of multilayers having lower concentrations in the outer periphery than inside.

CONSTITUTION: The P+ type drain diffused region 2 is composed of a P+ type high concentration region 2-a and a P type low concentration region 2-b having a concentration close to that of an N type substrate 1. In other words, a P+ type high concentration region 2-a similar to the conventional one is formed in the P type low concentration region 2-b. The P+ type source diffused region 3 is likewise composed of a P+ type high concentration region 3-a and a P type low concentration region 3-b. Besides, the N+ type source diffused region 6 and the N+ type drain diffused region 5 which have been formed in a P-well 7 substrate are constructed in such a manner that N+ type high concentration regions 5-a and 6-a are formed in N type low diffused regions 5-b and 6-b having concentrations close to that of the P-well substrate respectively.


Inventors:
TSUBOTA TOSHIO
Application Number:
JP15361384A
Publication Date:
February 15, 1986
Filing Date:
July 24, 1984
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L27/08; H01L27/092; H01L29/78; (IPC1-7): H01L27/08; H01L29/78
Attorney, Agent or Firm:
Uchihara Shin