SEMICONDUCTOR INTEGRATED CIRCUIT

Japanese Patent JPS592346

A

PURPOSE:To obtain an integrated circuit of high integration density, high speed, and low consumption power by a method wherein the width of at least a part of insulator isolation regions provided between a plurality of transistors equipped on a semiconductor wafer is constituted approximately equal to the depth or narrower than it. CONSTITUTION:A resistor is patterned, and a nitride film 203 and an oxide film 202 on an Si substrate 201 are etched. Next, ion implantation is performed with a resist 204 as the mask. After etching an amorphous region 205 generated as the result by reactive etching, plasma anodic oxidation is performed with the nitride film as the mask. Since the amorphous Si 205 is oxidized 2-5 times as fast as the single crystal Si 201 by the oxidation speed thereat, an oxide film region having a sectional structure approximately rectangular is formed. Thereafter, annealing is performed, the nitride film and the oxide film are removed by etching. The isolation region by above processes can take the depth larger than the width and can be formed with a small area, and accordingly is suitable for the formation of an integrated circuit of high density and high performance.

NISHIZAWA JIYUNICHI
OOMI TADAHIRO
OOSHIMA MASAKI

JP11242282A

January 07, 1984

June 28, 1982

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HANDOTAI KENKYU SHINKOKAI

H01L29/80; H01L21/22; H01L21/265; H01L21/302; H01L21/316; H01L21/76; H01L21/762; H01L21/8222; H01L27/06; H01L27/08; (IPC1-7): H01L21/265; H01L21/302; H01L21/95; H01L29/80

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