Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS598347
Kind Code:
A
Abstract:
PURPOSE:To prevent abnormal operation between wells due to a parasitic transistor with the substrate used as the base by newly providing a well between the adjacent wells. CONSTITUTION:A semiconductor integrated circuit device employing the P-N junction separation structure uses, for example, a P type substrate 3 and provides an N well 1 and an N well 2. Another well 4 is additionally provided between the wells 1 and 2 and a potential A of the well 4 is set higher than the potential of wells 1 and 2. Thereby, the collector of a parasitic N-P-N transistor which uses the P type substrate 3 as the base is formed by the N well 4. Accordingly, even when the base and emitter junction is forward biased, a collector current can be extracted from the well 4. Therefore, any influence is applied on the well 2 and junction between the wells 1 and 2 can be prevented. This well 4 may be a well containing elements and may be provided in such a manner as surrounding the well 1.
Inventors:
HASHIDA MITSUYOSHI
KAWARADA KUNIYASU
KAWARADA KUNIYASU
Application Number:
JP11679882A
Publication Date:
January 17, 1984
Filing Date:
July 07, 1982
Export Citation:
Assignee:
HITACHI LTD
NIPPON TELEGRAPH & TELEPHONE
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H01L21/331; H01L21/761; H01L29/73; (IPC1-7): H01L29/72
Domestic Patent References:
| JPS4844276A | 1973-06-26 |
Attorney, Agent or Firm:
Katsuo Ogawa
Next Patent: FABRICATION OF SEMICONDUCTOR DEVICE