Title:
MEMORY CONTROLLER
Document Type and Number:
Japanese Patent JPS584470
Kind Code:
A
Abstract:
PURPOSE:To speed up the execution of cutout and synthesis without path neck, by calculating the address of data to be transferred based on the length of required part and not required part of head address storing two-dimensional picture scanning data. CONSTITUTION:An address switch 10 of a memory controller 5 transmits data transmitted from an address bus 6 to a memory 4 when a mode selection signal 50/ transmitted from a control section 30 indicates the mode 1(a mode using a memory 4 as a main storage device of a central processor 3). When the signal 50/ indicates the mode 2(a mode using a memory 4 as a cutout/synthesis device of a partial diagram), a data 507 transmitted from an address controlling section 20 is transmitted to the memory 4 as an address data. The address controlling section 20 calculates the transferred address and transfer address at the mode 2.
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Inventors:
MACHIDA TETSUO
TSUHARA SUSUMU
TABATA KUNIAKI
OKADA YASUYUKI
TSUHARA SUSUMU
TABATA KUNIAKI
OKADA YASUYUKI
Application Number:
JP10123881A
Publication Date:
January 11, 1983
Filing Date:
July 01, 1981
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G11C7/00; G06F12/02; G06F13/28; G06T1/60; G06T3/00; (IPC1-7): G06F15/20; G11C7/00
Domestic Patent References:
| JPS5211730A | 1977-01-28 |
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)
Next Patent: AUTOMATIC WIPER