PURPOSE: To improve the transmission efficiency of a communication system and to reduce the cost by delaying variably geneation of an information bit for synchronizing signal so that the length of a serial data string to be transmitted and received is to be coped with thereby expanding the time slot.
CONSTITUTION: An AND gate 127 of a synchronizing code generator 113A to which a delay request signal SDM is led applies gate control to a reference clock signal C in response to the logical state of the signal SDM. Thus, the supply of a reference clock signal C is interrupted during the transmission of a serial data and th supply of the reference clock signal C is restarted after the end of transmission. Then the supply of a synchronizing sigal MV1 to the synchronizing sigal transmission line 111 is stopped until the transmission of serial data is finished and a reference clock signal C is generated during the transmission, the generation of the synchronizing signal MV1 is retarded until the end of transmission. Thus, the transmission of time slot is prolonged variably in response to the length of a serial data string and the data is transmitted without being disturbed by the clock of the synchronizing code.
FUTAMI TORU
SAKAGAMI ATSUSHI
