PURPOSE: To obtain a high speed parallel-serial converting circuit with economical constitution by using a shift register and a D flip-flop operated with a clock signal of a period 2T being twice the period T in which one bit of a video signal is outputted.
CONSTITUTION: An even number bit of a display data of 8-bit constitution inputted from an input terminal 14 is loaded to a shift register 3 by a load signal L and an odd number bit is loaded to a shift register 4. A display data is shifted by the registers 3, 4 according to a clock signal CK1 supplied from a terminal 11. Output signals (a), (b) of the registers 3, 4 are supplied sequentially to EX-OR gates 5, 6 and D flip-flop FF8, 9, 10. An EX-OR gate 7 ORes exclusively signals e, g outputted from the DFF 8 and 10 and outputs a video signal (h) converted into a serial signal.
KATAOKA MINORU
YONEKURA MIKIO
| JPS58146129A | 1983-08-31 |