Title:
TOGGLE FLIP-FLOP
Document Type and Number:
Japanese Patent JP3236235
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To test an optional toggle flip-flop by frequency-dividing and outputting inputted clock signals or outputting them without frequency-dividing them based on control signals inputted from the outside.
SOLUTION: A first circuit 10 generates and outputs first and second signals C and D based on the control signals TEST from the outside. A second circuit 20 outputs the clock signals CLK from the outside as they are and generates and outputs third and forth signals A and B based on the clock signals CLK and the signals C. A second gate group 30 outputs the clock signals CLK based on the clock signals CLK from the circuit 20 and the signals C and D from the circuit 10. A first gate group 40 frequency-divides and outputs the clock signals CLK or outputs them as they are based on the clock signals CLK from the gate group 30 and the signals A and B from the circuit 20. At the time of testing a circuit, just the control signals for outputting the inputted clock signals as they are inputted.
Inventors:
Makoto Wakasugi
Application Number:
JP3618997A
Publication Date:
December 10, 2001
Filing Date:
February 20, 1997
Export Citation:
Assignee:
NEC
International Classes:
H03K21/00; H03K21/40; H03K23/58; (IPC1-7): H03K21/00; H03K21/40; H03K23/58
Domestic Patent References:
| JP4361422A | ||||
| JP567949A | ||||
| JP5281308A | ||||
| JP2196520A | ||||
| JP4334124A |