PURPOSE: To implement optimum rewrite control for display by measuring a generated period of a request signal requesting transmission of display data outputted from a display device so as to surely detect a time change relating to the display revision operation of an FLC.
CONSTITUTION: A control signal from a CPU 1 is given to a memory controller 24 via a control bus driver 20. When the CPU address data used to access a video memory 25 for a prescribed time and the memory controller 24 is accessed by a different address, the controller 24 outputs the data only to a sampling counter 34, which counts the data. An interlace flag table memory 33 generates a signal to select one table from an address conversion table memory 37 based on the count value of the sampling counter 34 and a count value of an HSYNC measurement device 35 and the signal is given to the address conversion table memory 37.
SAKASHITA TATSUYA
NOBUTANI TOSHIYUKI
ONO KENICHIRO
TANAHASHI JUNICHI
MORIMOTO HAJIME
SHIMAKURA MASAMI
