Title:
TRACK AND HOLD CIRCUIT
Document Type and Number:
Japanese Patent JP2004129276
Kind Code:
A
Abstract:
To provide a track and hold circuit which is operated with a lower voltage and reduces distortions of hold waveforms.
The track and hold circuit which includes an NMOS transistor switch 603 and a hold capacitor 4 is provided for changing input signals in an in-phase manner to make a bulk potential of the NMOS transistor switch 603 lower than or equal with either that of the input signals or a source potential.
Inventors:
KAKIYA HISAO
Application Number:
JP2003346178A
Publication Date:
April 22, 2004
Filing Date:
October 03, 2003
Export Citation:
Assignee:
AGILENT TECHNOLOGIES JAPAN LTD
International Classes:
H03M1/12; G11C27/02; (IPC1-7): H03M1/12
Attorney, Agent or Firm:
Shoichi Okuyama
Arihara Koichi
Matsushima Tetsuo
Arihara Koichi
Matsushima Tetsuo
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