Title:
TRANSFER GATE AND DYNAMIC FREQUENCY DIVIDER CIRCUIT USING THE SAME
Document Type and Number:
Japanese Patent JP3242149
Kind Code:
B2
Abstract:
PURPOSE: To operate a frequency divider circuit at a lower frequency while ensuring high operating speed performance.
CONSTITUTION: D-MESFETs 1, 2 are connected in series and the gates of both the FETs 1, 2 are connected in common. Since the threshold voltage VTH1 of the D-MESFET1 is selected smaller than the threshold voltage VTH2 of the D-MESFET2, the D-MESFET1 acts like a variable resistor is which the resistance of the D-MESFET1 is low when an input signal IN to the gate is high and the D-MESFET2 is turned on and the resistance of the D-MESFET1 is high when the input signal IN to the gate is low and the D-MESFET2 is turned off. Thus, with a voltage at one terminal T1 of the transfer gate set to a low level, the voltage at the other terminal T2 set to a high level and the input signal set to a low level, a leakage current from the terminal T2 to the terminal T1 is reduced more than that of a conventional transfer gate while ensuring the high operation speed performance.
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Inventors:
Miki Kubota
Application Number:
JP13937592A
Publication Date:
December 25, 2001
Filing Date:
May 29, 1992
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03K17/687; H03K17/00; H03K17/66; H03K21/00; H03K23/52; H03K23/54; (IPC1-7): H03K17/00; H03K17/687; H03K23/54
Domestic Patent References:
| JP295014A | ||||
| JP3133213A | ||||
| JP6090425A | ||||
| JP6393217A | ||||
| JP2105627A | ||||
| JP62114538U |
Attorney, Agent or Firm:
Shinkichi Matsumoto
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