Title:
【発明の名称】レジスタ回路
Document Type and Number:
Japanese Patent JP3225528
Kind Code:
B2
Abstract:
An output terminal of a register circuit in an LSI circuit such as a microcomputer, etc. is set to be a set state and is reset to be a reset state in accordance with set and reset signals and a clock-stop signal which is generated at a stop mode. A stop current is measured to flow between a predetermined node of the register circuit at the set state, and between the predetermined node and a power supply at the reset state.
Inventors:
Ryuichi Sase
Application Number:
JP6172691A
Publication Date:
November 05, 2001
Filing Date:
March 26, 1991
Export Citation:
Assignee:
NEC
International Classes:
G06F1/24; G01R31/30; G06F15/78; H03K3/037; (IPC1-7): H03K3/037
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)