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Patent Searching and Data


Title:
TRANSFER SPEED DISCRIMINATION CIRCUIT
Document Type and Number:
Japanese Patent JPH04236533
Kind Code:
A
Abstract:

PURPOSE: To set automatically a transfer speed and to implement the reception by applying bipolar/unipolar conversion to a data from a line, extracting a clock, and counting number of consecutive '1s' in a data to discriminate the data transfer speed.

CONSTITUTION: A bipolar/unipolar conversion circuit CONV 1 extracts a clock from an input of a line whose clock speed is 6.3MHz to generate a unipolar signal, and an FF 2 latches the signal to prevent malfunction. The clock is counted by a count circuit 3 and reset when an output of the FF 2 goes to an L level. A speed discrimination circuit 4 discriminates it that a data of 6.3Mbps is received when number of consecutive 1s in the data is 15 or below. The circuit 4 discriminates it that a data of 1.5Mbps is received when number of consecutive 1s in the data is 16 or over and 111 or below. A selector 5 selects a relevant clock by the discrimination of the circuit 4 and a data reception circuit 6 receives the data. The 1.5M clocks are missing clocks.


Inventors:
KOSAKA SHINICHI
Application Number:
JP494691A
Publication Date:
August 25, 1992
Filing Date:
January 21, 1991
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04L7/04; H04L12/70; (IPC1-7): H04L7/04; H04L12/56
Attorney, Agent or Firm:
Shin Uchihara