To reduce current consumption by defining the operation of four circuits PRECHAGE, SENSE, EVAL and HOLD by means of a clock thereby enhancing the operating rate while limiting the read current to EVAL of evaluation period.

Transistors T3, T4 and T5, T6 constituting forward and inverted amplifiers, entering operating state for accessing a memory array by a SELECT waveform and responds to a bit line BIT by a BAL waveform during PRECHAGE phase, are clamped at the gates thereof and T7 is brought into nonconducting state by an EN waveform thus disconnecting the amplifiers from the ground. In SENS phase, the T7 is still nonconductive, the BIT is disconnected from the ground, gates of the amplifiers are interconnected through a T8 by the BAL waveform and the BIT is held at high level. In EVAL phase, the T7 is conducted by an EN waveform, the BIT is grounded through the amplifier and a current is taken out from a memory cell.