Title:
TRANSISTOR STRUCTURE FOR ERASABLE PROGRAMMABLE SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP3236054
Kind Code:
B2
Abstract:
PURPOSE: To provide an MOS transistor structure suitable for programming with standard TTL supply and produceable through a standard CMOS technology.
CONSTITUTION: A floating polysilicon gate spreads over a part of a channel through a thin oxide layer while having an extended part 18 insulated from a semiconductor substrate. A control gate 17 spreads from a source region 12 to a drain region 14 immediately thereon through a dielectric oxide layer while covering a part of the floating gate. A program gate 19 spreads immediately above the extended part 18 of the floating gate through the dielectric oxide layer to form an electric capacity along with the extended part of the floating gate. The program gate 19 and the control gate 17 have side fringe parts facing each other at an interval.
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Inventors:
Yang Bang Hout
Fid Fru Seneken
Hermann Mace
Fid Fru Seneken
Hermann Mace
Application Number:
JP4011492A
Publication Date:
December 04, 2001
Filing Date:
January 30, 1992
Export Citation:
Assignee:
INTERUNIVERSITAIR MICRO-ELEKTRONICA CENTRUM VZW
International Classes:
H01L21/8247; G11C16/04; G11C16/10; H01L27/115; H01L27/11526; H01L29/788; H01L29/792; H01L27/105; (IPC1-7): H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP6242459A | ||||
| JP2246165A | ||||
| JP3268364A | ||||
| JP322484A | ||||
| JP2240968A | ||||
| JP2110981A | ||||
| JP1192092A | ||||
| JP57104262A |
Attorney, Agent or Firm:
Kaoru Aoyama (4 people outside)
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