Title:
TRANSMISSION DEVICE AND METHOD FOR CONTROLLING FIFO CIRCUIT
Document Type and Number:
Japanese Patent JP2016130921
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To suppress generation of a signal error due to variations in phase of a writing clock without increasing the size of a memory of a FIFO circuit.SOLUTION: The transmission device includes: a writing pointer controlling unit generating a writing pointer, using a writing clock regenerated from a data signal; a reading clock generating unit generating a reading clock; a reading pointer controlling unit generating a reading pointer, using the reading clock; a memory in which a data signal is written into a bit specified by the writing pointer and a data signal is read from a bit specified by the reading pointer; a detecting unit detecting a usage rate of the memory based on difference between the writing pointer and the reading pointer; and a frequency controlling unit generating a frequency control signal changing the frequency of the reading clock if the usage rate is out of an acceptable range specified in advance.SELECTED DRAWING: Figure 2
Inventors:
KUWATA NAOKI
Application Number:
JP2015004530A
Publication Date:
July 21, 2016
Filing Date:
January 13, 2015
Export Citation:
Assignee:
FUJITSU OPTICAL COMPONENTS LTD
International Classes:
G06F13/38; G06F1/12; G06F13/42
Attorney, Agent or Firm:
Yoshiyuki Osuga
virtue Tamio Ei
virtue Tamio Ei
Previous Patent: Drive-through system
Next Patent: METHOD FOR MANUFACTURING TOUCH INPUT SENSOR, AND PHOTOSENSITIVE CONDUCTIVE FILM
Next Patent: METHOD FOR MANUFACTURING TOUCH INPUT SENSOR, AND PHOTOSENSITIVE CONDUCTIVE FILM