To establish and hold synchronization to reception signals by transmitting more information under given band width and code sequence length.

The information 1 is provided with the double bit speed of the information 2 and converted into the parallel signal of 2 bits in a serial/ parallel converter 10. The M sequence of 7 bits outputted by an M sequence generator 18 is delayed for one chip in a delay device 20 and the output of the delay device 20 and the output of the M sequence generator 18 are inputted to a selector 22. The information 2 as a selection signal is inputted to the selector 22, the output of the delay device 20 or the output of the M sequence generator 18 is selected corresponding to the value and the M sequence phase modulated by the information 2 is outputted. The output of the selector 22 is impressed to the other input of a multiplier 14. I phase signals and Q phase signals respectively directly spread by the M sequence and the M sequence phase modulated by the information 2 in the multipliers 12 and 14 are QPSK (4-phase shift keying) modulated in a quadrature modulator 24 and transmitted.