TRANSPORT TRAY, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND MANUFACTURING DEVICE FOR SEMICONDUCTOR DEVICE

Japanese Patent JP2022191679

A

To suppress a variation in the quality of a group of products manufactured using a transport tray.SOLUTION: A transport tray 1 includes a group of piece trays 20 and a frame 10. Each of the piece trays 20 has a tray portion 21 and an ear portion 22 with a lower end 24 positioned higher than its back surface 23. The frame 10 includes an upper surface 11, a lower surface 12, and a contact portion 11a that can abut against the lower ends 24 of the ear portions 22 when the tray portion 21 is arranged inside an opening portion 14. The height from the lower surface 12 of the frame 10 to the contact portion 11a is lower than the height from the rear surface 23 of the tray portion 21 to the lower end 24 of the ear portion 22. Even when there is a gap 400 between the lower surface 12 of the frame 10 and an installation surface 321 of a cooling plate 320, the tray portion 21 is displaced and the back surface 23 contacts the installation surface 321. Variations in solder cooling rate and occurrence of shrinkage cavities in bonding layers 220 and 240 of a processing targets 200 group mounted on the transport tray 1 are suppressed, and variations in the quality of an obtained product group are suppressed.SELECTED DRAWING: Figure 12

JPH0272695	HYBRID INTEGRATED CIRCUIT
JP2893226	METHOD FOR CONTINUOUSLY MANUFACTURING STRIP OF LEAD FRAME FOR INTEGRATED CIRCUIT DICE AND DEVICE THEREFOR

SANO SHINJI
TAKIZAWA NAOKI
SEKI TOMONORI
YOKOYAMA TAKESHI
MIYAZAWA YOSUKE

JP2021100049A

December 28, 2022

June 16, 2021

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FUJI ELECTRIC CO LTD

H01L21/48; B23K1/00; B23K3/00; F27D3/12; H01L21/50

Patent Attorney Corporation Fuso International Patent Office

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