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Title:
TRAPEZOID WAVE GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JPS61239715
Kind Code:
A
Abstract:

PURPOSE: To prevent effectively an output voltage from floating by short- circuiting the load resistance of a bootstrap circuit part by the series circuit of the amplifying transistor (TR) and diode of a mirror circuit part.

CONSTITUTION: When an input signal attains to zero, a TR Q1 turns off and a TR Q2 turns on to charge a capacitor C1 so that the right in a figure is positive. This is mirror integrating operation and a waveform which falls with good linearity is outputted. In this case, the resistance R3 is short-circuited through a diode D2 and the TR Q2, so when the TR Q2 is on, namely, when no input signal is supplied, the output voltage developed at an output terminal OUT is the negative-side voltage of a trapezoid wave generating circuit and prevented from floating.


Inventors:
AOKI TETSUO
KAWADA TOYOSHI
YAMAGUCHI HISASHI
GONDO HIROYUKI
Application Number:
JP8067785A
Publication Date:
October 25, 1986
Filing Date:
April 16, 1985
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03K4/501; H03K4/58; H03K4/94; (IPC1-7): H03K4/94
Attorney, Agent or Firm:
Koshiro Matsuoka



 
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