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Patent Searching and Data


Title:
TRAY FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH03169043
Kind Code:
A
Abstract:

PURPOSE: To prevent that a package is broken and that external leads are deformed and to enhance an operation property by making holes into which the external leads of a semiconductor integrated circuit device (IC) are inserted.

CONSTITUTION: A package positioning part 4, a hole 6 for external lead positioning use and a package pedestal 5 are formed in a tray main body 3 for IC use; when an IC is mounted, it is positioned by using the three parts. An IC external lead 2 is passed through the hole 6 for positioning use and is extracted to the outside; while the IC is in a state that it has been mounted in a tray for IC use, an electrical characteristic can be tested. In addition, a package holding part 7 is formed at the tray main body 3; when trays for IC use are piled up, the IC is positioned at four parts of the positioning part 4, the hole for positioning use, the package pedestal 5 and the package holding part 7. Thereby, a package is not broken, an external lead is not deformed and an operation property is enhanced.


Inventors:
MIURA TAKEO
Application Number:
JP31017389A
Publication Date:
July 22, 1991
Filing Date:
November 28, 1989
Export Citation:
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Assignee:
KYUSHU NIPPON ELECTRIC
International Classes:
H01L21/673; H01L21/68; (IPC1-7): H01L21/68
Attorney, Agent or Firm:
Uchihara Shin