Title:
半導体集積記憶回路及びラッチ回路のトリミング方法
Document Type and Number:
Japanese Patent JP4908472
Kind Code:
B2
Abstract:
A latch circuit includes first and second inverters connected in a cross-coupling manner at a first node and a second node. A voltage application circuit applies a hot carrier generation voltage for generating hot carrier at a transistor included in the first inverter or the second inverter. An inverting circuit generates an inversion signal as an inverted signal of an amplified signal provided from the latch circuit to the bit line pair to provide the inversion signal to the first node and the second node.
Inventors:
Atsushi Kawasumi
Application Number:
JP2008216198A
Publication Date:
April 04, 2012
Filing Date:
August 26, 2008
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C11/419; G11C11/41; G11C11/412; G11C11/413; H03K3/356
Domestic Patent References:
| JP2005276315A | ||||
| JP2005353106A | ||||
| JP2004127499A | ||||
| JP2003045190A | ||||
| JP6076582A | ||||
| JP2000311491A |
Attorney, Agent or Firm:
Fujiwara Yasutaka