Title:
TTL TO ECL/CML CONVERSION CIRCUIT HAVING DIFFERENTIAL OUTPUT TERMINAL
Document Type and Number:
Japanese Patent JPH0389623
Kind Code:
A
Abstract:
PURPOSE: To provide a conversion circuit capable of applying voltage, reducing output swing, narrowing a transition area and supplying a complementary or differential output by means of 1st and 2nd gate transistor(TR) elements of a differential amplifier which is integral with 1st and 2nd branch circuits of a current mirror. CONSTITUTION: The differential amplifier gates constituted of 1st and 2nd gate TR elements Q2, Q3 act cooperatively with the current mirror circuit in a conversion circuit. On a TTL input terminal, a node A is raised to 2VBE or 2ϕ TTL input threshold voltage level together with transition to a TTL logic input signal high potential level. The element Q3 is turned off, and a 3rd current component 1ϕ/R6 flowing through the element Q3 is turned off. A mechanism, based on a cooperative action between the current mirror circuit and the differential amplifier gate circuit gives a complementary ECL output by alternately switching the elements Q2, Q3.
Inventors:
JIYURIO AARU ESUTORAADA
Application Number:
JP22016790A
Publication Date:
April 15, 1991
Filing Date:
August 23, 1990
Export Citation:
Assignee:
NAT SEMICONDUCTOR CORP
International Classes:
H03K19/018; (IPC1-7): H03K19/018
Attorney, Agent or Firm:
Kazuo Kobashi (1 person outside)
Next Patent: JPH0389624