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Title:
TWO-STAGE SAMPLE/HOLD CIRCUIT
Document Type and Number:
Japanese Patent JPS60101799
Kind Code:
A
Abstract:

PURPOSE: To reduce power consumption through simple constitution by driving the current source of a buffer circuit only at the timing of plural sampling pulses.

CONSTITUTION: Depletion type FETs 111 and 131 are used and a sampling pulse is supplied to the gate of an enhancement type FET141. Further, a depletion type FET151 is used and a sampling pulse SP' is supplied to the gate of an enhancement type FET191 provided in parallel to the FET141. Other stages are constituted similarly. Then, the FETs 141 and 191 are off while no sampling pulse is supplied, and no current flows. When a sampling pulse is supplied, the FETs 111, 131, and 151 transfer a display signal efficiently and the FETs 141 and 191 operate in a saturation area and serves as constant current sources. Consequently, the current value in sampling is equalized to that in reading operation and the pulses SP' and SP are used as they are.


Inventors:
SONEDA MITSUO
HAYASHI YUUJI
Application Number:
JP20948983A
Publication Date:
June 05, 1985
Filing Date:
November 08, 1983
Export Citation:
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Assignee:
SONY CORP
International Classes:
H03M9/00; G11C27/02; (IPC1-7): H03M9/00
Attorney, Agent or Firm:
Sada Ito



 
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