Title:
TWO'S COMPLEMENT PULSE WIDTH MODULATOR AND METHOD FOR PULSE WIDTH MODULATING TWO'S COMPLEMENT
Document Type and Number:
Japanese Patent JP3297242
Kind Code:
B2
Abstract:
PURPOSE: To provide a pulse width modulator(PWM) which can directly accept data from the bus of a data processor in a simple configuration according to input data of two's completion.
CONSTITUTION: A PWM 20 receives a two's complement input number and separates a code bit from a remaining less significant bits. The PWM converts these bits to an unsigned number corresponding to the code bit. Corresponding to the output of a counter 30 being equal to the unsigned number, a comparator 41 supplies a compare output signal. A output circuit 25 supplies 1st and 2nd pulse width modulated signals for a time length determined by the output of the comparator corresponding to whether the code bit is positive or negative. The PWM converts a negative two's complete number to the unsigned number by making the less significant bits into one's complement, and the output circuit keeps the 2nd pulse width modulated signal active during one additional clock cycle for complete transformation to the two's complement without necessity in carry opeartion.
Inventors:
Yaia Obark
Heinrick Iosab
Effie Oryan
Heinrick Iosab
Effie Oryan
Application Number:
JP4129595A
Publication Date:
July 02, 2002
Filing Date:
February 06, 1995
Export Citation:
Assignee:
MOTOROLA INCORPORATED
International Classes:
H03K7/08; H03M5/08; (IPC1-7): H03M5/08; H03K7/08
Domestic Patent References:
| JP6245216A | ||||
| JP63211811A | ||||
| JP4133515A | ||||
| JP2292631A |
Attorney, Agent or Firm:
Yoshiaki Ikeuchi
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