To simplify a configuration for limiting a voltage to be applied between a gate and a source of each of transistors in an output circuit or a configuration for reducing an amplitude of a control signal to be input to a unit circuit.
A unit circuit J includes a first P-channel transistor, a second P-channel transistor, a first N-channel transistor and a second N-channel transistor which are connected in series between a power line 101 and a ground line 103. A first output signal V1 is then output from a first output terminal. A potential of the first output signal V1 becomes VDD while the first P-channel transistor is ON, and becomes VREF+Vtp2 while the first P-channel transistor is OFF. A second output signal V2 is output from a second output terminal. A potential of the second output signal V2 becomes GND while the second N-channel transistor is ON, and becomes VREF-Vtn1 while the second N-channel transistor is OFF.
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Yashiro Hitoshi
Taro Takahashi