Title:
DDRメモリデバイスのデータ出力のデューティサイクル制御及び正確な調整のための複数の電圧制御された遅延ラインの利用
Document Type and Number:
Japanese Patent JP4718576
Kind Code:
B2
Abstract:
A DLL circuit uses a rising edge DLL to align the rising edge of the output data to the system clock and a falling edge DLL to align the falling edge of the output data. The DLL circuit does not use the falling edge of the input clock to provide a reference for the falling edge DLL. The DLL circuit uses the rising edge of a first reference clock (a buffered version of the input clock) to align the rising edge of the output data. An additional DLL is used to generate a precise second reference clock that is delayed by exactly one-half period of the first reference clock to align the falling edge of the output data. Any variation in the duty cycle of the input clock or the input clock buffer does not effect the duty cycle of the output data.
Inventors:
John Dee Hytley
Application Number:
JP2008102571A
Publication Date:
July 06, 2011
Filing Date:
April 10, 2008
Export Citation:
Assignee:
Promos Technologies Pte Ltd
International Classes:
G11C11/4076; G11C11/407; H03K5/06; H03L7/081
Domestic Patent References:
| JP2001320273A | ||||
| JP2002290214A | ||||
| JP11205102A | ||||
| JP2003272379A | ||||
| JP9321614A |
Attorney, Agent or Firm:
Tadahiko Ito
Shinsuke Onuki
Tadashige Ito
Shinsuke Onuki
Tadashige Ito