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Title:
VARIABLE CLOCK-PERIOD PROCESSOR
Document Type and Number:
Japanese Patent JPS57109053
Kind Code:
A
Abstract:

PURPOSE: To increase processing performance by making a processing cycle variable, by controlling the oscillation frequency of the basic clock generation part of a processor by control bits of a microprogram.

CONSTITUTION: A sequencer 1 is operated by a clock from a clock generating oscillator 5 to supply an address to a microprogram memory 2 in accordance with an address supplied from an external address source, and a program which corresponds to the address is sent to a pipeline register 3. A next-address controller 10, an arithmetic part 6, etc., are operated corresponding to respective control bits in the register 3 to send the result of arithmetic performed between the arithmetic part 6 and a data register 7 to the register 7, an address register 8, and a status register 9, thereby performing the transfer of data with external equipment. Then, a controller 10 is operated by pieces of information from the registers 9 and 3 to supply a program control signal to the sequencer 1, and a processing cycle is varied to increase processing performance.


Inventors:
IZUMI TSUNETADA
Application Number:
JP18547680A
Publication Date:
July 07, 1982
Filing Date:
December 26, 1980
Export Citation:
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Assignee:
RICOH KK
International Classes:
G04F5/00; G04G3/00; G06F1/08; G06F9/22; (IPC1-7): G04F5/00; G04G3/00; G06F1/04; G06F9/22



 
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