Title:
VARIABLE DELAY CIRCUIT AND PHASE ADJUSTMENT CIRCUIT
Document Type and Number:
Japanese Patent JP3560319
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a variable delay circuit where a lower limit of a delay time to be set is not fluctuated independently of a range of a settable delay time and precision of a resolving time.
SOLUTION: The variable delay circuit 101 is provided with delay circuits 102-1-102-n that delay an input signal Fin and a selection circuit 103 that selects one of outputs of the delay circuits 102-1-102-n and outputs the selected output as an output signal Fout. The delay circuit 102-k delays the input signal Fin by a 1st delay time. The delay circuit 102-m delays the input signal Fin by a 2nd delay time longer than the 1st delay time. A difference between the 1st delay time and the 2nd delay time is shorter than a minimum delay time td that can be set by the delay circuit 102-k.
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Inventors:
Toru Iwata
Hiroyuki Yamauchi
Hiroyuki Yamauchi
Application Number:
JP9559799A
Publication Date:
September 02, 2004
Filing Date:
April 01, 1999
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F1/10; G11C11/407; G11C11/4076; H03K5/13; H03L7/081; (IPC1-7): H03K5/13; G06F1/10; H03L7/081
Domestic Patent References:
| JP8274600A | ||||
| JP8274602A | ||||
| JP9046195A | ||||
| JP5259845A | ||||
| JP5129911A | ||||
| JP3130678A |
Attorney, Agent or Firm:
Hidesaku Yamamoto