PURPOSE: To select a desired delay with a sufficiently small chip area in the case of circuit integration by devising the circuit such that delay quantities selected over a wide range are set by using a minimum number of delay elements.

CONSTITUTION: The circuit is provided with plural delay elements (e.g. 21-24), a basic delay (d) is set to the element 21 and a delay of 2n with respect to the basic delay (d) is set respectively to other elements 22-24 sequentially (2-; n=1, 2, 3V). Thus, the delay quantities are given in a range of 0-15d at an interval of (d) by devising the delay elements to be combined optionally. That is, 14 sets of switching elements 30 subjected to circuit integration comprising transfer gates or the like are provided and each control input is extracted externally as the delay setting terminal. Then a prescribed control signal is applied to the terminal to combine and connect the delay elements 21-24 thereby setting a desired delay.