PURPOSE: To heighten the upper limit of an operable input frequency by enabling the output terminal of each data latch flip-flop to be connected to only one input.

CONSTITUTION: The true signal output terminal Q1 and the auxiliary signal output terminal, the inverse of Q1 of a first data latch flip-flop DFF1 are connected to the data input terminal D21 and the comparison data input terminal Dr2 of a second data latch flip-flop DFF2, respectively, and to an output circuit. In such a case, since a true signal and an axiliary signal are used, output amplitude is doubled as the ordinary one, that is equivalent to the constitution of the output H fan-out 1 of the first data latch flip-flop DFF1. Also, the constitution of the output of all other data latch flip-flops DFF2, DFF3 at the rear stage are formed in the same constitution as the fan-out 1. Thereby, it is possible to attain the simplification of circuit configuration, the high stabilization of an operation, and acceleration, and to heighten the upper limit of the operable input frequency.