PURPOSE: To allow the circuit to contribute to the high processing speed for a data processing unit.

CONSTITUTION: When an operating mode signal MC is at a low level, 1/2 frequency division is conducted and when the signal MC is at a high level, 1/3 frequency division is conducted. In the case of 1/3 frequency division, a 2nd feedback signal S2 from an output of a shift register 2 is fed back to a clock input C1 of a 1/2 frequency divider circuit 1 through a 1st gate circuit 3 and a 2nd gate circuit 4. Since no setup time is in existence in the clock input C1, the period of a clock signal CK is decided by taking only a delay time of the shift register 2, the 1st gate circuit 3 and the 2nd gate circuit 4 into account. That is, since the period of the clock signal CK has been decided by taking also the setup time of a conventional 1/2 frequency dividing circuit 1 into account, a margin time to reduce the period of the clock signal CK is extended more in comparison with above and normal frequency division is conducted even when the period of the clock signal CK is reduced more than that of the conventional circuit.